The present technology relates to a storage controlling apparatus. More particularly, the present technology relates to a storage controlling apparatus, a storage apparatus and an information processing system for a nonvolatile memory and a processing method for the storage controlling apparatus, storage apparatus and information processing system as well as a program for causing a computer to execute the processing method.
In a semiconductor memory such as a NAND flash memory or a ReRAM (Resistance RAM), writing and erasure are carried out collectively into and from memory cells connected to a selected word line. Upon writing or erasure of data, a method of carrying out verify reading out after a writing operation or an erasure operation into or from the memory cells is used in order to ensure the reliability of data. If a writing operation into or an erasure operation from memory cells and verify reading out are executed only once, then the writing operation or the erasure operation does not sometimes end correctly by an influence of a dispersion arising from a fabrication process. In this instance, a writing operation or an erasure operation and verify reading out are executed repetitively by a plural number of times.
On the other hand, in order to correctly record or read out data into or from a NAND flash memory or a ReRAM, the internal circuit of a memory chip or a memory controller has an error correction function. Also a method of utilizing the error correction function such that appearance of some errors is permitted to decrease the number of times of repetition to speed up writing or erasure of data has been proposed. Such a method as just described is disclosed, for example, in Japanese Patent Laid-Open No. Hei 06-131884, Japanese Patent Laid-Open No. 2002-048783 or Japanese Patent Laid-Open No. Hei 10-222995.